1. Field of the Invention
The present invention relates to the field of fabrication of integrated circuits, and, more particularly, to a semiconductor device having a polysilicon line structure with metal silicide portions and a method of forming polysilicon line structures with metal silicide portions on active regions of semiconductor devices.
2. Description of the Related Art
In the most common field effect transistors, a gate structure essentially comprises a gate electrode formed above a gate insulation layer, wherein polysilicon is often selected as the material for forming the gate electrode for several reasons.
For instance, polysilicon exhibits high compatibility with the subsequent high temperature processes. Moreover, the polysilicon interface with thermal silicon dioxide is well understood and electrically stable. Furthermore, polysilicon is more reliable than, for example, aluminum gate materials, and polysilicon can be deposited conformally over step topography.
However problems arise when polysilicon is used as a gate material due to its higher resistivity when compared to, e.g., aluminum. In fact, the defects in the grain boundaries of the polysilicon, together with the decreased overall free carrier concentration, cause an increased resistivity of polysilicon lines, such as the gate electrode.
Even when doped at the highest practical concentration, a 0.5xcexc thick polysilicon film has a sheet resistance of about 20 xcexa9sq. compared to 0.05 xcexa9sq. for 0.5xcexc thick aluminum film. The resulting high values of interconnect polysilicon line resistance can lead to relatively long RC time constants (i.e., long propagation delays) and serious DC voltage variations within VLSI (very large scale integration) circuits.
To overcome this drawback, several solutions have been proposed and developed in the art. Among these solutions, the formation of metal silicides on the top of the polysilicon gate structure has proven to be the most reliable one for obtaining the lowest resistance values.
A typical prior art method of forming metal silicides on silicon-containing regions, such as the gate electrode of a CMOS transistor, will be described in the following with reference to FIGS. 1a-1f. 
In FIG. 1a, reference 1 relates to an arbitrary section of a substrate, for instance a silicon wafer, on which a CMOS transistor is to be formed. In particular, in FIG. 1a, reference 2 relates to isolation structures which have been previously formed. These isolation structures divide the section of the substrate 1 into two portions on which the PMOS transistor and the NMOS transistor are to be formed, respectively. In the particular case depicted in FIGS. 1a-1f, the PMOS portion is depicted on the left side of the figures and the NMOS portion on the right side of the figures.
Moreover, in FIG. 1a, references 3p and 3n relate to the gate polysilicon electrodes of the PMOS and NMOS transistors, respectively. References 4p and 4n relate to oxide spacers formed on the sidewalls of the polysilicon gate electrodes. References 6p and 6n relate to the gate insulation layers in the PMOS region and the NMOS region, respectively. Finally, references 5lp and 5ln relate to lightly doped regions in the PMOS and NMOS portions of the transistor, respectively.
In FIGS. 1b-1f, the features already described with reference to FIG. 1a are identified by the same reference numerals. Additionally, in FIG. 1b, a dielectric liner 7 is depicted, for instance an oxide liner, and a layer 9 of a dielectric material, for instance a nitride layer 9, is formed on said dielectric liner 7.
In FIG. 1c, references 4p, 7p and 9p relate to a dielectric spacer, a dielectric liner, and a further dielectric spacer formed on the sidewalls of the gate electrode 3p of the PMOS transistor, respectively. Also, in FIG. 1c, references 4n, 7n and 9n relate to a dielectric spacer, a dielectric liner, and a further dielectric spacer formed on the sidewalls of the gate electrode 3n of the NMOS transistor, respectively. Furthermore, in FIG. 1c, references 5fp and 5fn relate to doped regions of the PMOS and NMOS portions of the substrate, respectively, with said doped regions 5fp and 5fn having a predefined final dopant concentration.
In FIG. 1d, reference 8 relates to a metal layer deposited on the substrate. In FIG. 1e, references 8sp and 8sn relate to metal silicide layers formed on the gate electrodes 3p and 3n and the doped regions 5fp and 5fn of the PMOS and NMOS portions, respectively. Finally, in FIG. 1f, there is depicted an enlarged view of the portion of FIG. 1c encircled by the dashed line of FIG. 1c. 
During the first step, as depicted in FIG. 1a, of the prior art method of forming metal suicides, lightly doped regions 5lp and 5ln are formed. To this end, an ion implantation step is carried out for implanting dopants (for instance, boron and or arsenic) at a low concentration into the regions of the substrate not covered by the gate structures 3p and 3n. An annealing step is then carried out for diffusing the implanted dopants into the substrate. Once the lightly doped regions 5lp and 5ln have been formed, dielectric spacers 4p and 4n are formed on the sidewalls of the gate electrodes 3p and 3n. Usually, the dielectric spacers 4p and 4n are formed by first conformally depositing a dielectric layer (not depicted in the figures) on the substrate and anisotropically etching the dielectric layer so as to remove the dielectric layer from the upper surface of the gate electrodes 3p and 3n and from the lightly doped regions 5lp and 5ln. In this way, dielectric spacers 4p and 4n of a substantially uniform thickness are formed on the sidewalls of the gate electrodes 3p and 3n. 
In a next step, as depicted in FIG. 1b, the dielectric liner 7 and the dielectric layer 9 are subsequently formed on a substrate. For instance, the dielectric liner 7 can be an oxide liner and the dielectric layer 9 can be a nitride layer. The liner 7 and the layer 9 are conformally formed and exhibit a substantially uniform thickness, with the dielectric layer 9 being thicker than the dielectric liner 7.
The prior art method is then continued by anisotropically etching the layer 9, the liner 7 and the dielectric spacers 4p and 4n. In particular, as depicted in FIG. 1c, the anisotropic etching process is not stopped once the dielectric layer 9 and the dielectric liner 7 are removed from the regions 5fp and 5fn and the upper surface of the polysilicon gate electrodes 3p and 3n, but is carried out so as to overetch the dielectric layer 9, the dielectric liner 7 and the dielectric spacers 4p and 4n until the upper sidewall portions of the polysilicon gate electrodes 3p and 3n are exposed. In this way, the dielectric spacers 4p and 4n, the liner spacers 7p and 7n, and the nitride spacers 9p and 9n are formed as depicted in FIG. 1c. Once the spacers have been formed, a further implantation step is eventually carried out with the purpose of further modifying the dopant concentration in the portions of the substrate not covered by the spacers so as to form doped regions as identified in FIG. 1c by the dotted-dashed lines.
In a next step, as depicted in FIG. 1d, a metal layer 8 is deposited on the substrate 1. For instance, titanium or cobalt or any other refractory metal such as tantalum, tungsten, zirconium, nickel or a combination thereof may be selected for forming the metal layer 8. Due to the fact that the dielectric sidewall spacers 4p, 7p, 9p and 4n, 7n and 9n do not cover the sidewalls of the polysilicon gate electrodes 3p and 3n completely, i.e., the upper sidewall portions of the polysilicon electrodes 3p and 3n have been exposed during the previous anisotropic overetching step, portions of the metal layer 8 come into contact with the exposed upper sidewall portions of the polysilicon gate electrodes 3p and 3n. Accordingly, a metal-silicon interface is formed, not only on the upper surface of the polysilicon gate electrode 3p and 3n and the doped regions 5fp and 5fn, but a metal-silicon interface is also formed at the upper sidewall portions of the polysilicon gate electrodes 3p and 3n. 
Subsequently, in a next step, as depicted in FIG. 1e, a thermal treatment (about 650xc2x0 C. for titanium; other temperatures may be selected depending on the metal used) is carried out to react the metal and the silicon exposed on the doped regions 5fp and 5fn and the polysilicon gate electrodes 3p and 3n. As a result, vertical diffusion of the polysilicon and silicide-forming metal occurs at the upper surface of the polysilicon gate electrodes 3p and 3ln and the doped regions 5fp and 5fn, along with horizontal diffusion at the metal-polysilicon interface in correspondence with the upper sidewall portions of the polysilicon gate electrodes 3p and 3n. The thermal treatment, therefore, results in the formation of the metal silicide compound layers 8sp and 8sn (see FIG. 1e); the thickness of the layers 8sp and 8sn depends on the type of metal, the initial layer thickness of the metal layer 8 and on the process parameters of the heat treatment. As depicted in FIG. 1e, the metal silicide layers 8sp and 8sn comprise a horizontal portion covering the upper surface of the polysilicon lines 3p and 3n, together with vertical portions extending on the exposed upper sidewall portions of the polysilicon lines 3p and 3n. The vertical portions of the metal silicide layers 8sp and 8sn help in reducing the total sheet resistance of the polysilicon lines 3p and 3n, and are of particular relevance in those applications in which very narrow polysilicon lines are required.
The process is then continued with the removal of the unreacted metal with an etching step (not depicted in the figures), leaving behind the metal silicide compound layers 8sp and 8sn. For instance, a wet etching step can be carried out in which a bath of H2O:H2O2:NH4OH is used that removes substantially only the unreacted metal.
The prior art method described above has accomplished satisfactory results for devices having minimum feature sizes of 0.5xcexc and more. The above method, however, is not completely adequate to compensate for the increase of the polysilicon sheet resistance, which arises in cases of deep sub-micron devices, i.e., with features sizes equal to or less than 0.25xcexc.
The reasons for this can be explained as follows. At the end of the etching step depicted in FIG. 1c, the dielectric spacers 4p and 4n and the dielectric liners 7p and 7n are not etched away as schematically depicted therein. The real situation at the end of this etching step may be illustrated in a more representative manner in FIG. 1f. In particular, as is apparent from FIG. 1f, the upper sidewall portions of the gate electrodes 3p and 3n (indicated as xe2x80x9crecessxe2x80x9d in FIG. 1f) are not completely exposed but are still partially covered by the remaining dielectric spacers 4p and the dielectric liners 7p which extend vertically beyond the remaining dielectric spacers 9p. This is due to the fact that a single etching step is carried out for etching the dielectric layer 9, the liner 7 and the dielectric spacers 4p of FIG. 1b. Accordingly, since the dielectric layer 9, the liner 7 and the dielectric spacers 4p exhibit different etch rates (with the dielectric layer 9 exhibiting the highest etching rate), the spacers 4p and the liner 7 are not removed from the sidewalls of the polysilicon line 3p to the same extent as the spacers 9p. As a result, as depicted in FIG. 1f, the upper sidewall portions of the polysilicon lines 3p and 3n from which the spacers 9p are removed (corresponding to the xe2x80x9crecessxe2x80x9d of FIG. 1f) are not completely exposed but residual spacers 4p and liners 7p still partially cover the upper sidewall portions.
Accordingly, the benefit of overetching the spacers 9p is limited by the remaining dielectric material on the gate upper sidewalls consisting of the spacers 4p and the liners 7p, since silicidation by horizontal metal diffusion through the upper sidewalls is hindered by the residual dielectric material. Therefore, relatively small upper sidewall portions of the polysilicon gate electrodes 3p and 3n are converted into a silicide so that metal silicide layers featuring relatively short vertical portions are formed. Accordingly, the metal silicide layers may not significantly contribute to reducing the total sheet resistance of the polysilicon lines 3p and 3n. 
Since the trend toward increasing miniaturization of the devices manufacturable on a substrate will continue in years to come, it clearly results that the formation of metal silicide layers on the top of gate polysilicon lines according to the prior art methods would render it very difficult to realize polysilicon line structures featuring resistances in conformity with the electrical performances required.
Accordingly, in view of the problems explained above, it would be desirable to provide a method that may solve or reduce one or more of these problems. In particular, it would be desirable to provide a method of forming polysilicon line structures featuring metal silicide layers of increased dimensions, thus exhibiting low sheet resistance and ensuring high electrical performance of the devices with such polysilicon line structures.
Generally, the present invention is based on the consideration that metal silicide layers or regions of increased dimensions can be realized if upper sidewall portions of polysilicon lines, such as gate electrodes, interconnect lines and the like, substantially free from oxide residuals, are produced when forming the sidewall spacers. The silicidation through the sidewalls of the polysilicon line is then no longer blocked by residual oxide, and metal silicide layers featuring vertical portions of increased dimensions can be formed on the polysilicon line structures. Accordingly, the sheet resistance of the polysilicon line structures is substantially determined by the silicide layers. This is of particular relevance for those applications where gate structures of field effect transistors have to be formed. In fact, as previously stated, the trend towards ever-increasing miniaturization of the devices requires field effect transistors featuring ever-decreasing channel lengths, i.e., ever-decreasing bottom critical dimensions of the gate structures formed on the channels. Accordingly, the need arises for forming gate structures featuring bottom critical dimensions as small as required by the miniaturization trend, but featuring metal silicide layers large enough for compensating the high values of sheet resistance arising from the miniaturization of the devices.
For this purpose, according to one embodiment, the present invention relates to a method comprising forming at least one feature of a silicon-containing semiconductive material above a substrate, wherein the feature has sidewalls and an upper surface. The method further comprises forming a dielectric layer on the sidewalls of the feature, wherein the dielectric layer covers portions of the substrate adjacent the sidewalls. The method further comprises introducing dopant material into at least the portions of the substrate not covered by the feature and the dielectric layer and removing the dielectric layer so as to expose the sidewalls of the feature. Finally, the method comprises forming spacer elements adjacent a portion of the sidewalls so that the elements cover less than all of the sidewalls and define exposed upper sidewall portions.
According to another embodiment, the method comprises forming at least one polysilicon line above an active region of a substrate and introducing a first dopant material into at least one portion of the active region not covered by the polysilicon line and into the polysilicon line. Moreover, the method comprises forming a dielectric layer on the sidewalls of the polysilicon line, wherein the dielectric layer covers portions of the active region adjacent the sidewalls, and introduces a second dopant material into at least the portions of the active region not covered by the polysilicon line and the dielectric layers. The method further comprises removing the dielectric layer so as to expose the sidewalls of the polysilicon line and forming spacer elements adjacent a portion of the sidewalls, wherein the elements cover less than all of the sidewalls and define exposed upper sidewall portions.
According to a further embodiment, the method comprises forming at least one polysilicon line above a substrate and introducing a first dopant material at a first predefined concentration into at least one portion of the substrate not covered by the polysilicon line and into the polysilicon line. The method further comprises forming a dielectric layer on the sidewalls of the polysilicon line, wherein the dielectric layer covers portions of the substrate adjacent the sidewalls. Moreover, the method comprises introducing a second dopant material at a second predefined concentration higher than the first concentration into at least the portions of the substrate not covered by the polysilicon line and the dielectric layer. Finally, the method comprises removing the dielectric layer so as to expose the sidewalls of the polysilicon line, and forming spacer elements adjacent a portion of the sidewalls, wherein the elements cover less than all of the sidewalls and define exposed upper sidewall portions. A metal silicide layer is formed on at least the upper surface and the exposed upper sidewall portions of the polysilicon line.
In still another embodiment of the present invention, the method comprises forming at least one polysilicon line above the substrate and introducing a first dopant material at the first predefined concentration in at least one portion of the substrate not covered by the polysilicon line and in the polysilicon line. The method further comprises forming a dielectric layer on the sidewalls of the polysilicon line, wherein the dielectric layer covers portions of the substrate adjacent the sidewalls. A second dopant material at a second predefined concentration lower than the first concentration is introduced into at least the portions of the substrate not covered by the polysilicon line and the dielectric layer. The method finally comprises removing the dielectric layer so as to expose the sidewalls of the polysilicon line, forming spacer elements adjacent a portion of the sidewalls, wherein the elements cover less than all of the sidewalls and define exposed upper sidewall portions, and forming a metal silicide layer on at least the upper surface and the exposed upper sidewall portions of the polysilicon line.